The present invention relates to a flip-flop circuit that operates at a high speed and can be configured with a small number of transistors. More particularly, the present invention relates to a flip-flop circuit capable of selectively storing one of a plurality of data inputs or a flip-flop circuit with a scan function.
Flip-flop circuits account for a significant part, among other logic circuits in a semiconductor integrated circuit, in terms of the area, the power consumption and the critical path delay. Accordingly, there is a demand for a flip-flop circuit with a smaller area, a lower power consumption and a higher speed. Particularly, scan flip-flop circuits are often used for easy testing of LSIs being designed, and it is therefore important to realize a scan flip-flop circuit with a smaller area, a lower power consumption and a higher speed.
Recently, a flip-flop circuit is proposed in the art for high-speed applications, which employs a latch circuit capable of latching in data within a period of a pulse width that is shorter than the clock cycle. Conventional flip-flop circuits having such configurations will now be described with reference to circuit diagrams of FIGS. 8 and 9.
FIG. 8 shows a scan flip-flop circuit of a type called “SDFF (Semi-Dynamic Flip-Flop)”, including an input section using a dynamic circuit and an output section using a static circuit. This is one exemplary configuration described in U.S. Pat. No. 5,898,330 (hereinafter referred to as “Conventional Example 1”).
In FIG. 8, D denotes a data signal, CK a clock signal, SI a test input signal, SCAN a test selection signal, Q an output signal, VDD a VDD power supply, and GND a GND potential.
N20 to N23 are N-type transistors. A series of N-type transistors N20 and N21 and another series of N-type transistors N22 and N23 are connected in parallel to each other to form a selector circuit. In this configuration, the control of the N-type transistor N21 with the data signal D and the control of the N-type transistor N23 with the test input signal SI is exclusively selected by the N-type transistor N20, which is controlled by the test selection signal SCAN inverted through an inverter circuit INV7, and the N-type transistor N22, which is controlled by the test selection signal SCAN.
P1 is a P-type transistor whose source is connected to the VDD power supply, and N3 is an N-type transistor whose source is connected to the GND potential. The gates of these transistors each receive a clock signal CK. The N-type transistor N1 is connected in series with the drain of the P-type transistor P1, and the selector circuit as described above is inserted in series between the source of the N-type transistor N1 and the drain of the N-type transistor N3. The connection node between the drain of the P-type transistor P1 and the drain of the N-type transistor N1 is X1. The output terminal of a 2-input NAND circuit ND1 is connected to the gate of the N-type transistor N1. One input terminal of the NAND circuit ND1 is connected to the node X1, and the other input terminal receives the clock signal CK being delayed through two inverter circuits INV1 and INV2. The connection node between the inverter circuit INV2 and the other input terminal of the NAND circuit ND1 is CKD.
The node X1 is connected to the gate of a P-type transistor P2, whose source is connected to the VDD power supply, and to the gate of an N-type transistor N5, whose source is connected to the GND potential. An N-type transistor N4, whose gate receives the clock signal CK, is inserted in series between the P-type transistor P2 and the N-type transistor N5. The output potential obtained from the connection node between the P-type transistor P2 and the N-type transistor N4 is the output signal Q.
The latch circuit including inverter circuits INV3 and INV4 is connected to the node X1, and the latch circuit including inverter circuits INV5 and INV6 is connected to the drain of the P-type transistor P2 outputting the output signal Q.
Next, the operation of the scan flip-flop circuit having such a configuration will be described.
First, the operation where the test selection signal SCAN is at a low level, i.e., where the data signal D is being selected, will be described.
During a period in which the clock signal CK is at the low level, the potential of the node X1 goes high as the P-type transistor P1 is turned ON. Then, the N-type transistor N4 and the P-type transistor P2 are cut off, whereby the output signal Q is held at the previous value.
Then, when the clock signal CK transitions to a high level, the potential of the node CKD does not transition to the high level immediately but does so after the delay through the inverter circuits INV1 and INV2. During the period in which the clock signal CK is at the high level and the potential of the node CKD is at the low level (hereinafter referred to as the “evaluation period”), the N-type transistor N1 is ON. Therefore, if the data signal D is at the high level in this period, the node X1 transitions from the high level to the low level, and the output signal Q is transitioned to the high level by the P-type transistor P2. If the input signal D is at the low level in the evaluation period, the node X1 remains at the high level and the output signal Q is transitioned to the low level by the N-type transistors N4 and N5.
Then, the circuit transitions to a state where the clock signal CK is at the high level and the potential of the node CKD is at the high level (hereinafter referred to as the “hold period”). In this period, if the potential of the node X1 is at the high level, the N-type transistor N1 is cut off by the 2-input NAND circuit ND1, whereby the high level potential is held by the inverter circuits INV3 and INV4 without being influenced by the value of the data signal D. Where the circuit enters the hold period with the node X1 being at the low level, since the P-type transistor P1 is cut off, the potential of the node X1 is held at the low level by the inverter circuits INV3 and INV4, irrespective of the value of the input signal D.
Normally, an inverter circuit includes two transistors and a 2-input NAND circuit includes four transistors. Accordingly, the flip-flop circuit of Conventional Example 1 shown in FIG. 8 can be realized with a total of 28 transistors.
FIG. 9 shows an alternative configuration of a scan flip-flop circuit of the type called “SDFF” (hereinafter referred to as “Conventional Example 2”). Like elements to those shown in FIG. 8 are denoted by like reference numerals and will not be further described below.
The scan flip-flop circuit of FIG. 9 has the same function as that of FIG. 8. However, the scan flip-flop circuit of FIG. 9 does not include the N-type transistor N1 and the NAND circuit ND1, which are provided in the circuit of FIG. 8 for holding the potential of the node X1 at the high level in the hold period. Instead, the scan flip-flop circuit of FIG. 9 additionally includes an AND/OR inverter circuit AOI1 and an AND/OR inverter circuit AOI2. The AND/OR inverter circuit AOI1 includes a 2-input AND circuit and an OR inverter circuit receiving the output from the 2-input AND circuit and the test selection signal SCAN, and AND/OR inverter circuit AOI2 similarly includes a 2-input AND circuit and an OR inverter circuit receiving the output from the 2-input AND circuit and a signal obtained by inverting the test selection signal SCAN through the inverter circuit INV7.
Thus, with the data signal D being at the low level, if the clock signal CK rises from the low level to the high level, the potential of the node CKD transitions from the low level to the high level in the hold period, whereby the N-type transistors N20 and N22 are cut off, irrespective of the value of the test selection signal SCAN. Therefore, the potential of the node X1 is held at the high level, irrespective of the value of the data signal D, thus providing a similar function to that of the N-type transistor N1 of FIG. 8.
Since an AND/OR inverter circuit normally includes six transistors, the circuit shown in FIG. 9 includes a total of 35 transistors.
However, in the scan flip-flop circuit shown in FIG. 8, a maximum of four N-type transistors are connected together in series, thereby increasing the delay time.
In the scan flip-flop circuit shown in FIG. 9, the number of transistors to be connected together in series is three, thus realizing a shorter delay time as compared with the circuit of FIG. 8. However, the circuit of FIG. 9 requires as many as 35 transistors.
Moreover, with the scan flip-flop circuits of FIGS. 8 and 9, if the circuit attempts to take in the test input signal SI being low when the clock signal CK is transitioning from low to high, the test input signal SI needs to be held at the low level from when the clock starts rising until the output from the NAND circuit ND1 (or the AND/OR inverter circuit AOI2) is transitioned from high to low by the inverter circuit INV2, after the clock is delayed through the inverter circuits INV1 and INV2, to thereby cut off the transistor N1 (or the transistor N22). Thus, the flip-flop circuits have a long hold time.